A multichip system embeds pluralities of memory chips operable in various applications, and a chipset rendering the memory chips to be usable in correspondence with their applications. The chipset includes a memory interface block with various forms in order to assist operations of the various memory chips in accordance with their usage.
In recent, as the capacity of data is increasing as such multimedia data, it highly demands for a multichip system which contains a memory chip with large storage capacity in a small area and a memory chip with high speedy data rate. Such a multichip system is advantageous to compensating the demerits of the high-density and large-capacity memory chips each other in designing its hardware architecture.
For example, a NAND flash memory chip employs an increment step-pulse programming (ISPP) scheme because it needs to narrow a distribution profile of cell threshold voltages and is conductive with very small cell string currents. Therefore, the NAND flash memory chip has a programming speed very slower than that of a volatile memory chip such as a DRAM chip and an SRAM chip. In order to overcome such a demerit of the NAND flash memory chip in a programming speed, data to be stored in the NAND flash memory chip is preliminarily stored in a volatile memory chip that is operable in a high speed of operation. To the contrary, it is also frequent to store data from a volatile memory chip into a nonvolatile memory chip such as the NAND flash memory chip.